From: David Abrahams (dave_at_[hidden])
Date: 2003-10-01 17:54:13
Stefan Seefeld <seefeld_at_[hidden]> writes:
> Andrei is only talking about registers, but not about CPU caches (L1,
> L2), or about memory barriers. IIRC, people in the end agreed that
> using volatile is by no means a guarantee for thread-safe access to
> memory, at least not in multi-processor architectures.
Yes, I was pretty sure that part of the article was bogus, but I'm
really interested in the other part.
-- Dave Abrahams Boost Consulting www.boost-consulting.com